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R12.4 Chemical Vapor Deposition Reactors

   

As discussed in Section 6.6, CVD is a very important process in the microelectronics industry. The fabrication of microelectronic devices may include as few as 30 or as many as 200 individual steps to produce chips with up to 10 6 transducers per chip. An abbreviated schematic of the steps involved in producing a typical computer chip is shown in Figure CD12-12.

Although we will focus on CVD, it is worthwhile to give an overview of microelectronic fabrication. Starting from the upper left we see that single crystal silicon ingots are grown in a Czochralski crystalizer, then sliced into wafers, and chemically and physically polished. These polished wafers serve as a starting material for a variety of microelectronic devices. A typical fabrication sequence is shown for processing the wafer beginning with the formation of an SiO 2 layer on top of the silicon. The SiO 2 layer may be formed either by oxidizing a silicon layer or by laying down a SiO 2 vapor deposition (CVD). Next the wafer is masked with a polymer photoresist (PR), a layer by chemical template with the pattern to be etched onto the SiO 2 layer is placed over the PR, and the wafer is exposed to ultraviolet irradiation. If the mask is a positive PR , the light will cause scission in the polymer so that the exposed areas will dissolve when the wafer is placed in the developer. On the other hand, when a negative PR mask is exposed to ultraviolet irradiation, cross-linking of the polymer chains occurs and the unexposed areas dissolve in the developer. The undeveloped portion of the PR (in either case) will protect the covered areas from etching.

Figure CD12-12
Microelectric Fabrication Steps

After the exposed areas of SiO 2 are etched to form trenches (either by wet etching (see Problem P5-12) or plasma etching), the remaining PR is removed. Next the wafer is placed in a furnace containing gas molecules of the desired dopant, which then diffuse into the exposed silicon. After diffusion of dopant to the desired depth in the wafer, it is removed and then covered with SiO 2 by CVD. The sequence of masking, etching, CVD, and metallization continues until the desired device is formed. A schematic of a final chip is shown in the lower right-hand corner of Figure CD12-12.

One of the key steps in the chip-making process is the deposition of different semiconductors and metals on the surface of the chip. This step can be achieved by CVD. CVD mechanisms were discussed in Chapter 10. Consequently, this section will focus on CVD reactors. A number of CVD reactor types have been used, such as barrel reactors, boat reactors, and horizontal and vertical reactors. A description of these reactors and modeling equations is given by Jensen.26

 

R12.4-B Fundamentals of CVD
   

One of the more common CVD reactors is the horizontal low-pressure CVD (LPCVD) reactor. This reactor operates at pressures of approximately 100 Pa. The main advantage of the LPCVD is its capability of processing a large number of wafers without detrimental effects to film uniformity. Owing to the large increases in the diffusion coefficient at low pressures (recall Table 11-2), surface reactions are more likely to be controlling than mass transfer. A schematic of a LPCVD boat reactor is shown in

     
   

Figure CD12-13
LPCVD boat reactor

     
    To illustrate LPCVD modeling we shall use a specific but simplified example, the deposition of silicon from a gas stream of SiH 2 . The reaction mechanism is
     
CVD reaction
sequence in silicon
deposition
  image 12eq256.gif
     
    Here we have assumed that the equilibrium for the dissociation of SiH discussed in Problem P10-12 lies far to the right.
The corresponding rate law is

image 12eq257.gif

     
    Recalling that the adsorption constants K 1 and K 2 decrease with increasing temperatures, an excellent approximation at high temperature is
     
    image 12eq258.gif
     
    Consequently, the deposition rate can be modeled as first-order in SiH 2 :
     
    image 12eq259.gif
    where ASiH 2 .
     
  Modeling Concepts. We shall model the axial flow in the annular region as being laminar. This assumption is reasonable because a typical Reynolds number for flow in a LPCVD reactor is less than 1. As the reactant gases flow through the annulus, the reactants diffuse from the annulus radially inward between the wafers to coat them. 27

The reacting gas flows through the annulus between the outer edges of the cylindrical wafers and the tube wall (see Figure CD12-14). The corresponding cross-sectional area of the annulus is

Flow in the
annulus

 

image 12eq260.gif
    where R t and R w are the radii of the tube and wafer, respectively. Because SiH 2 is being consumed by CVD, the mole fraction of SiH 2 (i.e., the reactant) in the annulus, y AA , decreases as the reactant flows down the length of the annulus.
    The reacting gases diffuse out of the annular region into the space between the wafers where the mole fraction is represented by y A . As molecules diffuse radially inward, some of them are adsorbed and deposited on the wafer surface. The reaction products then diffuse radially outward into the gas stream axially flowing in the annulus. This system can be analyzed in a manner analogous to flow through a packed catalyst bed where the reaction gases diffuse into the catalyst pellets. In this analysis we used an effectiveness factor to determine the overall rate of reaction per volume (or mass) of reactor bed. We can extend this idea to LPCVD reactors, where the reactants diffuse from the annular flow channel radially inward between the wafers.
     
   

Figure CD12-14
LPCVD boat reactor with peripherals
     

R12.4-C Effectiveness Factor for a LPCVD Reactor
   


Silicon will deposit on the wafers, the reactor walls, and on the boat support. Deposition on the walls and support will take place at the reactant concentrations in the annulus. However, the concentration of A between the wafers is less than the concentration in the annulus. Consequently, the rate of deposition on the wafer will be less than the rate at conditions in the annulus. Fortunately, these two concentrations can be related by the effectiveness factor. We can determine the effectiveness factor once the concentration profile in the region between the wafers is obtained.

     
     
    image 12eq261.gif
    where l is the distance between wafers and is the rate of disappearance of A at the concentration of A in the annular region, C AA . We now useto express the actual rate of reaction per unit surface area of wafer in terms of the rate of reaction at conditions in the annulus:
     
    image 12eq263.gif
     
    Letting a be the wafer surface area per unit volume of reactor, the rate of consumption of species A by the wafer per unit volume of reactor is
     
    image 12eq264.gif
     
    Example CD12-8
Diffusion Between Wafers

Accounting for
Si deposition
on the walls
and support

  Deposition on the Peripherals. Silicon will deposit on the walls of a reactor and on the boat support in addition to the wafers. This rate of deposition on the walls and support is
   
12eq284.gif
     
    Owing to high temperature and low pressure, radiation is the dominant heat transfer mechanism; therefor, small temperature differences exist between the wafer and reactor wall. Consequently, there is no need to couple the mole and energy balances for these small temperature gradients.
     
    Example CD12-9
CVD Boat Reactor